About: fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components

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An Entity of Type : schema:ScholarlyArticle, within Data Space : covidontheweb.inria.fr associated with source document(s)

Attributes	Values
type	Academic Article research paper schema:ScholarlyArticle
isDefinedBy	Covid-on-the-Web dataset
has title	fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components
Creator	Barrett, Clark Mann, Makai Daly, Ross Donovick, Caleb Hanrahan, Pat Herbst, Steven Horowitz, Mark Setaluri, Rajsekhar Stanley, Daniel Truong, Lenny Zhang, Keyi
Source	PMC
abstract	While hardware generators have drastically improved design productivity, they have introduced new challenges for the task of verification. To effectively cover the functionality of a sophisticated generator, verification engineers require tools that provide the flexibility of metaprogramming. However, flexibility alone is not enough; components must also be portable in order to encourage the proliferation of verification libraries as well as enable new methodologies. This paper introduces fault, a Python embedded hardware verification language that aims to empower design teams to realize the full potential of generators.
has issue date	2020-06-13(xsd:dateTime)
bibo:doi	10.1007/978-3-030-53288-8_19
has license	cc-by
sha1sum (hex)	d1ac0e9a5fba30bad758c5f24b957b5bfc4b1e7a
schema:url	https://doi.org/10.1007/978-3-030-53288-8_19
resource representing a document's title	fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components
has PubMed Central identifier	PMC7363199
schema:publication	Computer Aided Verification
resource representing a document's body	covid:d1ac0e9a5fba30bad758c5f24b957b5bfc4b1e7a#body_text
is schema:about of	named entity 'flexibility' named entity 'CHALLENGES' named entity 'METHODOLOGIES' named entity 'PYTHON' named entity 'GENERATOR' named entity 'PROVIDE' named entity 'EMBEDDED' named entity 'PORTABLE' named entity 'SPECIFIC' named entity 'portable' named entity 'However' named entity 'teams' named entity 'productivity' named entity 'generators' named entity 'fault' named entity 'embedded hardware' named entity 'metaprogramming' named entity 'hardware verification language' named entity 'hardware generators' named entity 'design teams' named entity 'Hardware Verification' named entity 'Embedded Domain-Specific Language' named entity 'metaprogram' named entity 'Python' named entity 'input port' named entity 'Python' named entity 'eval' named entity 'Python library' named entity 'verilator' named entity 'model checkers' named entity 'test bench' named entity 'automation' named entity 'magma' named entity 'Python' named entity 'eval' named entity 'language design' named entity 'mixed-signal' named entity 'Python code' named entity 'Verilog' named entity 'abstraction' named entity 'hardware verification' named entity 'mixed-signal circuits' named entity 'logic' named entity 'interoperability' named entity 'compiler' named entity 'integration tests' named entity 'component reuse' named entity 'Verilog' named entity 'design teams' named entity 'Verilog-AMS' named entity 'rejection sampling' named entity 'intermediate representation' named entity 'Verilog-AMS' named entity 'API' named entity 'mixed-signal' named entity 'metaprogramming' named entity 'exit code' named entity 'domain-specific language' named entity 'Verilog-AMS' named entity 'compiler' named entity 'runtime performance' named entity 'formal verification' named entity 'reusable component' named entity 'open-source' named entity 'ALU' named entity 'PWL' named entity 'intermediate representation' named entity 'control structure' named entity 'open-source' named entity 'Python' named entity 'Python program' named entity 'control flow' named entity 'metaprogramming'

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