About: covid:PMC7343417

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An Entity of Type : owl:Thing, within Data Space : covidontheweb.inria.fr associated with source document(s)

Attributes	Values
Creator	Altmeyer, Sebastian Amslinger, Rico Haas, Florian Piatka, Christian Pionteck, Thilo Trinitis, Carsten Ungerer, Theo Weis, Sebastian Brinkmann, André Karl, Wolfgang Lankes, Stefan Tomforde, Sven
is schema:about of	named entity 'Embedded Systems' named entity 'transactional memory' named entity 'transactional memory' named entity 'memory capacity' named entity 'L1 cache' named entity 'High-performance' named entity 'L2 cache' named entity 'L1 cache' named entity 'running in parallel' named entity 'mixed criticality' named entity 'transactional memory' named entity 'speedup' named entity 'run time' named entity 'transactional execution' named entity 'instruction set architecture' named entity 'usability' named entity 'scheduler' named entity 'L1 cache' named entity 'benchmark suite' named entity 'HTM' named entity 'transactional execution' named entity 'cache lines' named entity 'transactional execution' named entity 'multicore' named entity 'committed transactions' named entity 'real-time strategies' named entity 'Thread synchronization' named entity 'Intel TSX' named entity 'ARM' named entity 'ARMv7' named entity 'Concurrent' named entity 'cache line' named entity 'IBM' named entity 'synchronization primitive' named entity 'mixed criticality' named entity 'cache line' named entity 'write access' named entity 'meta data' named entity 'speedup' named entity 'cache line' named entity 'ported' named entity 'power consumption' named entity 'speedup' named entity 'register files' named entity 'L1 cache' named entity 'run in parallel' named entity 'POSIX' named entity 'fault tolerance' named entity 'committed transactions' named entity 'L2 cache' named entity 'L1 cache' named entity 'transactional memory' named entity 'transactional memory' named entity 'transactional memory' named entity 'x86' named entity 'multicore' named entity 'speedup' named entity 'embedded systems' named entity 'benchmark suite' named entity 'embedded systems' named entity 'multicore' named entity 'Intel' named entity 'transactional memory' named entity 'physical hardware' named entity 'benchmark suite' named entity 'cache coherence protocol' named entity 'cache hierarchy' named entity 'HTM' named entity 'smartphones' named entity '64 bit' named entity 'embedded systems' named entity 'transactional memory' named entity 'embedded systems' named entity 'upper bound' named entity 'usability' named entity 'computational power' named entity 'memory hierarchy' named entity 'Concurrent' named entity 'parallelization' named entity 'speedup' named entity '11.6' named entity 'CPUs' named entity 'L1 cache' named entity 'embedded systems' named entity 'high performance' named entity '2, 7, 8' named entity 'transactional memory' named entity 'transactional memory'

Attributes

Values

Creator

Altmeyer, Sebastian
Amslinger, Rico
Haas, Florian
Piatka, Christian
Pionteck, Thilo
Trinitis, Carsten
Ungerer, Theo
Weis, Sebastian
Brinkmann, André
Karl, Wolfgang
Lankes, Stefan
Tomforde, Sven

is schema:about of

named entity 'Embedded Systems'
named entity 'transactional memory'
named entity 'transactional memory'
named entity 'memory capacity'
named entity 'L1 cache'
named entity 'High-performance'
named entity 'L2 cache'
named entity 'L1 cache'
named entity 'running in parallel'
named entity 'mixed criticality'
named entity 'transactional memory'
named entity 'speedup'
named entity 'run time'
named entity 'transactional execution'
named entity 'instruction set architecture'
named entity 'usability'
named entity 'scheduler'
named entity 'L1 cache'
named entity 'benchmark suite'
named entity 'HTM'
named entity 'transactional execution'
named entity 'cache lines'
named entity 'transactional execution'
named entity 'multicore'
named entity 'committed transactions'
named entity 'real-time strategies'
named entity 'Thread synchronization'
named entity 'Intel TSX'
named entity 'ARM'
named entity 'ARMv7'
named entity 'Concurrent'
named entity 'cache line'
named entity 'IBM'
named entity 'synchronization primitive'
named entity 'mixed criticality'
named entity 'cache line'
named entity 'write access'
named entity 'meta data'
named entity 'speedup'
named entity 'cache line'
named entity 'ported'
named entity 'power consumption'
named entity 'speedup'
named entity 'register files'
named entity 'L1 cache'
named entity 'run in parallel'
named entity 'POSIX'
named entity 'fault tolerance'
named entity 'committed transactions'
named entity 'L2 cache'
named entity 'L1 cache'
named entity 'transactional memory'
named entity 'transactional memory'
named entity 'transactional memory'
named entity 'x86'
named entity 'multicore'
named entity 'speedup'
named entity 'embedded systems'
named entity 'benchmark suite'
named entity 'embedded systems'
named entity 'multicore'
named entity 'Intel'
named entity 'transactional memory'
named entity 'physical hardware'
named entity 'benchmark suite'
named entity 'cache coherence protocol'
named entity 'cache hierarchy'
named entity 'HTM'
named entity 'smartphones'
named entity '64 bit'
named entity 'embedded systems'
named entity 'transactional memory'
named entity 'embedded systems'
named entity 'upper bound'
named entity 'usability'
named entity 'computational power'
named entity 'memory hierarchy'
named entity 'Concurrent'
named entity 'parallelization'
named entity 'speedup'
named entity '11.6'
named entity 'CPUs'
named entity 'L1 cache'
named entity 'embedded systems'
named entity 'high performance'
named entity '2, 7, 8'
named entity 'transactional memory'
named entity 'transactional memory'

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